]> www.infradead.org Git - users/jedix/linux-maple.git/commit
iommu/riscv: Command and fault queue support
authorTomasz Jeznach <tjeznach@rivosinc.com>
Wed, 16 Oct 2024 06:52:18 +0000 (23:52 -0700)
committerJoerg Roedel <jroedel@suse.de>
Tue, 29 Oct 2024 08:46:29 +0000 (09:46 +0100)
commit856c0cfe5c5f6a2cc8d995872eb67bff9c68c57c
tree19ac985f98b4e52e175b64a20c9839fce36212d9
parent1bac10c557adb29891f938c0b5ff93f37e9ba8b1
iommu/riscv: Command and fault queue support

Introduce device command submission and fault reporting queues,
as described in Chapter 3.1 and 3.2 of the RISC-V IOMMU Architecture
Specification.

Command and fault queues are instantiated in contiguous system memory
local to IOMMU device domain, or mapped from fixed I/O space provided
by the hardware implementation. Detection of the location and maximum
allowed size of the queue utilize WARL properties of queue base control
register. Driver implementation will try to allocate up to 128KB of
system memory, while respecting hardware supported maximum queue size.

Interrupts allocation is based on interrupt vectors availability and
distributed to all queues in simple round-robin fashion. For hardware
Implementation with fixed event type to interrupt vector assignment
IVEC WARL property is used to discover such mappings.

Address translation, command and queue fault handling in this change
is limited to simple fault reporting without taking any action.

Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/c4735fb6829053eff37ce1bcca4906192afd743c.1729059707.git.tjeznach@rivosinc.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/riscv/iommu-bits.h
drivers/iommu/riscv/iommu.c
drivers/iommu/riscv/iommu.h