]> www.infradead.org Git - users/jedix/linux-maple.git/commit
PCI: Add dev->has_secondary_link to track downstream PCIe links
authorYijing Wang <wangyijing@huawei.com>
Thu, 21 May 2015 07:05:02 +0000 (15:05 +0800)
committerChuck Anderson <chuck.anderson@oracle.com>
Thu, 26 May 2016 22:46:08 +0000 (15:46 -0700)
commit834c35402c34a9f43c68563de57d4cc2c5398465
treeddb770dfbb3bd03d5907721be83082b900152520
parent87cea4d3367cc8b2749180222230a57e1540f028
PCI: Add dev->has_secondary_link to track downstream PCIe links

Orabug: 23331066

[ Upstream commit d0751b98dfa391f862e02dc36a233a54615e3f1d ]

A PCIe Port is an interface to a Link.  A Root Port is a PCI-PCI bridge in
a Root Complex and has a Link on its secondary (downstream) side.  For
other Ports, the Link may be on either the upstream (closer to the Root
Complex) or downstream side of the Port.

The usual topology has a Root Port connected to an Upstream Port.  We
previously assumed this was the only possible topology, and that a
Downstream Port's Link was always on its downstream side, like this:

                  +---------------------+
  +------+        |          Downstream |
  | Root |        | Upstream       Port +--Link--
  | Port +--Link--+ Port                |
  +------+        |          Downstream |
                  |                Port +--Link--
                  +---------------------+

But systems do exist (see URL below) where the Root Port is connected to a
Downstream Port.  In this case, a Downstream Port's Link may be on either
the upstream or downstream side:

                  +---------------------+
  +------+        |            Upstream |
  | Root |        | Downstream     Port +--Link--
  | Port +--Link--+ Port                |
  +------+        |          Downstream |
                  |                Port +--Link--
                  +---------------------+

We can't use the Port type to determine which side the Link is on, so add a
bit in struct pci_dev to keep track.

A Root Port's Link is always on the Port's secondary side.  A component
(Endpoint or Port) on the other end of the Link obviously has the Link on
its upstream side.  If that component is a Port, it is part of a Switch or
a Bridge.  A Bridge has a PCI or PCI-X bus on its secondary side, not a
Link.  The internal bus of a Switch connects the Port to another Port whose
Link is on the downstream side.

[bhelgaas: changelog, comment, cache "type", use if/else]
Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
(cherry picked from commit 517a021fdba44206722c85bd9267dabd67475fa6)

Signed-off-by: Dan Duval <dan.duval@oracle.com>
drivers/pci/probe.c
include/linux/pci.h