www.infradead.org Git - users/willy/xarray.git/commit

author	Ville Syrjälä <ville.syrjala@linux.intel.com>
	Wed, 17 Apr 2024 15:12:11 +0000 (18:12 +0300)
committer	Ville Syrjälä <ville.syrjala@linux.intel.com>
	Fri, 19 Apr 2024 16:45:42 +0000 (19:45 +0300)
commit	8034945d1a5e56f7eb1885cdd21801f93153b5a6
tree	bee5cbf67c321bba39036cfa72d79119861253cd	tree
parent	8221a6229a8509bf0e51046d43dd8d3d85cdf8dd	commit \| diff

drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk

Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.

v2: Adjust gvt accordingly

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417151211.32135-1-ville.syrjala@linux.intel.com

drivers/gpu/drm/i915/display/intel_dpio_phy.c		diff \| blob \| history
drivers/gpu/drm/i915/display/intel_dpll_mgr.c		diff \| blob \| history
drivers/gpu/drm/i915/gvt/handlers.c		diff \| blob \| history
drivers/gpu/drm/i915/i915_reg.h		diff \| blob \| history
drivers/gpu/drm/i915/intel_gvt_mmio_table.c		diff \| blob \| history