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arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
authorAlex Bennée <alex.bennee@linaro.org>
Thu, 1 Mar 2018 11:05:53 +0000 (11:05 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 1 Mar 2018 11:13:59 +0000 (11:13 +0000)
commit7d4dd1a73a023f75c893623710e43743501b318e
tree7a5857827f35e5ea168c8b6199e22a707c13a476tree
parent2df581304193d70eaf0d22cf4cb4613f74b6e59bcommit | diff
arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16

I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c diff | blob | history
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