]> www.infradead.org Git - users/hch/configfs.git/commit
net: phy: introduce core support for phy-mode = "10g-qxgmii"
authorVladimir Oltean <vladimir.oltean@nxp.com>
Sat, 15 Jun 2024 12:00:27 +0000 (20:00 +0800)
committerPaolo Abeni <pabeni@redhat.com>
Tue, 18 Jun 2024 11:28:26 +0000 (13:28 +0200)
commit777b8afb8179155353ec14b1d8153122410aba29
tree8d65d57afc43502f02fec7126a1c821e50531b94
parent041cc86b3653cbcdf6ab96c2f2ae34f3d0a99b0a
net: phy: introduce core support for phy-mode = "10g-qxgmii"

10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
specification. It uses the same signaling as USXGMII, but it multiplexes
4 ports over the link, resulting in a maximum speed of 2.5G per port.

Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
they could get away just fine with that thus far. But there is a need to
distinguish between the 2 as far as SerDes drivers are concerned.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Documentation/networking/phy.rst
drivers/net/phy/phy-core.c
drivers/net/phy/phylink.c
include/linux/phy.h
include/linux/phylink.h