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irqchip/renesas-rzv2h: Update TSSR_TIEN macro
authorBiju Das <biju.das.jz@bp.renesas.com>
Mon, 24 Feb 2025 13:11:26 +0000 (13:11 +0000)
committerThomas Gleixner <tglx@linutronix.de>
Wed, 26 Feb 2025 10:59:50 +0000 (11:59 +0100)
commit76c3b774734feb8224b78721e0c67a54760a75c5
tree0b22f107e2e9d6625fb13336c5b2425153be9db3tree
parent1a6ebcc10b138a6c55f8df2cf6cc630ddabe3cabcommit | diff
irqchip/renesas-rzv2h: Update TSSR_TIEN macro

On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace the
macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, _field_width) for supporting both
these SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/all/20250224131253.134199-11-biju.das.jz@bp.renesas.com
drivers/irqchip/irq-renesas-rzv2h.c diff | blob | history
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