]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: Add Zvkg ISA extension support
authorNazar Kazakov <nazar.kazakov@codethink.co.uk>
Tue, 11 Jul 2023 16:59:11 +0000 (00:59 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 11 Sep 2023 01:45:55 +0000 (11:45 +1000)
commit767eb03548f75b1d7c446305dd5bdb074c0b6d8f
tree54ddd1bd72e8b62d9c81cba68f4325742503571e
parent2350881c44bdc7c72de6525dbfadddb93ebfd146
target/riscv: Add Zvkg ISA extension support

This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:

* vgmul.vv
* vghsh.vv

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvkg property]
[max.chou@sifive.com: Replaced uint by int for cross win32 build]
Message-ID: <20230711165917.2629866-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvvk.c.inc
target/riscv/vcrypto_helper.c