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clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs
authorTaniya Das <quic_tdas@quicinc.com>
Wed, 4 Dec 2024 19:37:16 +0000 (11:37 -0800)
committerBjorn Andersson <andersson@kernel.org>
Mon, 6 Jan 2025 16:29:27 +0000 (10:29 -0600)
commit745d755b8551319a100adafc6e776a2766102ea9
treea42de8b1468ab3a188e537d9815f310046807fc7tree
parentc035a9e265dd80a018cfde0fd07ceca9e1d07c98commit | diff
clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs

Add clock ops for Taycan PLL, add the register offsets for supporting
the PLL.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-4-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/clk-alpha-pll.c diff | blob | history
drivers/clk/qcom/clk-alpha-pll.h diff | blob | history
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