]> www.infradead.org Git - users/jedix/linux-maple.git/commit
rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
authorStafford Horne <shorne@gmail.com>
Tue, 14 Jan 2025 17:07:21 +0000 (17:07 +0000)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 14 Feb 2025 21:06:36 +0000 (13:06 -0800)
commit713e788c0e07e185fd44dd581f74855ef149722f
treeed994ab5a620e5840df8c2b9a8f2e70f67b9d87c
parent599c44cd21f4967774e0acf58f734009be4aea9a
rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm

When working on OpenRISC support for restartable sequences I noticed
and fixed these two issues with the riscv support bits.

 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
   passed to the macro.  Fix this by adding 'inc' to the list of macro
   arguments.
 2 The inline asm input constraints for 'inc' and 'off' use "er",  The
   riscv gcc port does not have an "e" constraint, this looks to be
   copied from the x86 port.  Fix this by just using an "r" constraint.

I have compile tested this only for riscv.  However, the same fixes I
use in the OpenRISC rseq selftests and everything passes with no issues.

Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")
Signed-off-by: Stafford Horne <shorne@gmail.com>
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Acked-by: Shuah Khan <skhan@linuxfoundation.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20250114170721.3613280-1-shorne@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
tools/testing/selftests/rseq/rseq-riscv-bits.h
tools/testing/selftests/rseq/rseq-riscv.h