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clk: meson: c3: pll: fix frac maximum value for hifi_pll
authorChuan Liu <chuan.liu@amlogic.com>
Mon, 9 Sep 2024 10:08:57 +0000 (18:08 +0800)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 30 Sep 2024 09:27:42 +0000 (11:27 +0200)
commit6e442c2d7825a0758f00610d94822cfa82a258b9
tree80f0f520374d72059cc90f762938e81b7b0a9975tree
parentc939154e8417d5e04865ff0e45ec8e78592b262dcommit | diff
clk: meson: c3: pll: fix frac maximum value for hifi_pll

The fractional denominator of C3's hifi_pll fractional multiplier is
fixed to 100000.

Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/c3-pll.c diff | blob | history
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