]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: Add cycle & instret privilege mode filtering definitions
authorKaiwen Xue <kaiwenx@rivosinc.com>
Thu, 11 Jul 2024 22:31:07 +0000 (15:31 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 18 Jul 2024 02:08:44 +0000 (12:08 +1000)
commit6d1e3893cfaeedb47a16edbb766fcc0c7907ab94
tree423e8dd6ccc255abc9be9ecc548f34bdd7b3c875
parent251dccc09af363900436656461151681687e2470
target/riscv: Add cycle & instret privilege mode filtering definitions

This adds the definitions for ISA extension smcntrpmf.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-4-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h