]> www.infradead.org Git - users/jedix/linux-maple.git/commit
cxl/pci: Update Port GPF timeout only when the first EP attaching
authorLi Ming <ming.li@zohomail.com>
Sun, 23 Mar 2025 09:31:09 +0000 (17:31 +0800)
committerDave Jiang <dave.jiang@intel.com>
Wed, 9 Apr 2025 19:48:18 +0000 (12:48 -0700)
commit6af941db6a60a27209bdb2da1a3a780574d617fe
treef1dd8b319030574e3ee80f20d1355a5648c2ac90
parent87d2de042c602e12230283cd40fa604b881e12f7
cxl/pci: Update Port GPF timeout only when the first EP attaching

update_gpf_port_dvsec() is used to update GPF Phase timeout, if a CXL
switch is under a CXL root port, update_gpf_port_dvsec() will be invoked
on the CXL root port when each cxl memory device under the CXL switch is
attaching. It is enough to be invoked once, others are redundant.

When the first EP attaching, it always triggers its ancestor dports to
locate their own Port GPF DVSEC. The change is that invoking
update_gpf_port_dvsec() on these ancestor dports after ancestor dport
locating a Port GPF DVSEC. It guarantees that update_gpf_port_dvsec() is
invoked on a dport only happens during the first EP attaching.

Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Tested-by: Davidlohr Bueso <dave@stgolabs.net>
Link: https://patch.msgid.link/20250323093110.233040-3-ming.li@zohomail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/pci.c