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spi: intel: Fix the offset to get the 64K erase opcode
authorMauro Lima <mauro.lima@eclypsium.com>
Wed, 12 Oct 2022 15:21:35 +0000 (12:21 -0300)
committerMark Brown <broonie@kernel.org>
Thu, 13 Oct 2022 12:01:37 +0000 (13:01 +0100)
commit6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06
treeaefb6073741de020f21d9d039982cc7442659276tree
parent5302e1ff315b40dfc9bb3f08911f5a788cc1de01commit | diff
spi: intel: Fix the offset to get the 64K erase opcode

According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.

Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-intel.c diff | blob | history
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