]> www.infradead.org Git - users/willy/xarray.git/commit
drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
authorGustavo Sousa <gustavo.sousa@intel.com>
Tue, 12 Mar 2024 16:36:35 +0000 (13:36 -0300)
committerLucas De Marchi <lucas.demarchi@intel.com>
Wed, 13 Mar 2024 12:46:45 +0000 (05:46 -0700)
commit66a0e0681392420b326f00ba732e6bda099eda29
tree6d73db4e472f0e59f5123d04c0bf596feee1a30a
parent452269e2f0ea180a4bc39fd4643df7fe2ea0bb8e
drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()

As of Xe2LPD, it is now possible to select the source of the MDCLK
as either the CD2XCLK or the CDCLK PLL.

Previous display IPs were hardcoded to use the CD2XCLK. For those, the
ratio between MDCLK and CDCLK remained constant, namely 2. For Xe2LPD,
when we select the CDCLK PLL as the source, the ratio will vary
according to the squashing configuration (since the cd2x divisor is
fixed for all supported configurations).

To help the transition to supporting changes in the ratio, extract the
function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic
and call it using 2 as hardcoded ratio. Upcoming changes will use that
function for updates in the ratio due to CDCLK changes.

Bspec: 50057, 69445, 49213, 68868
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240312163639.172321-5-gustavo.sousa@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/i915/display/skl_watermark.c