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clk: renesas: r9a07g044: Add P2 Clock support
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 26 Jun 2021 08:13:38 +0000 (09:13 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 12 Jul 2021 08:52:03 +0000 (10:52 +0200)
commit668756f7299d2d3c75add17cb415717e247450ef
tree04cb2c88c37ccd6d8186f651b8b97192ede808b4tree
parentfd8c3f6c36eb093039d4aeb20cceee00c7c6ba1acommit | diff
clk: renesas: r9a07g044: Add P2 Clock support

Add support for P2 clock which is sourced from pll3_div2_4_2.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
drivers/clk/renesas/renesas-rzg2l-cpg.h diff | blob | history
XArray, radix tree and IDR