Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next

Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next

* clk-amlogic:
  clk: meson: introduce symbol namespace for amlogic clocks
  clk: meson: axg-audio: add sm1 earcrx clocks
  clk: meson: axg-audio: setup regmap max_register based on the SoC
  dt-bindings: clock: axg-audio: add earcrx clock ids
  clk: meson: s4: pll: Constify struct regmap_config
  clk: meson: s4: peripherals: Constify struct regmap_config
  clk: meson: c3: pll: Constify struct regmap_config
  clk: meson: c3: peripherals: Constify struct regmap_config
  clk: meson: a1: pll: Constify struct regmap_config
  clk: meson: a1: peripherals: Constify struct regmap_config

* clk-microchip:
  clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
  clk: at91: sam9x7: add sam9x7 pmc driver
  dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
  clk: at91: sama7g5: move mux table macros to header file
  clk: at91: sam9x7: add support for HW PLL freq dividers
  clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
  dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller
  dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7

* clk-imx: (27 commits)
  clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
  clk: imx95: enable the clock of NETCMIX block control
  dt-bindings: clock: add RMII clock selection
  dt-bindings: clock: add i.MX95 NETCMIX block control
  clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
  clk: imx: composite-7ulp: Use NULL instead of 0
  clk: imx: add missing MODULE_DESCRIPTION() macros
  clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
  clk: imx: fracn-gppll: update rate table
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
  clk: imx: imx8mn: add sai7_ipg_clk clock settings
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost
  clk: imx: composite-7ulp: Check the PCC present bit
  ...