x86/bugs: rework x86_spec_ctrl_set to make its changes explicit

x86/bugs: rework x86_spec_ctrl_set to make its changes explicit

x86_spec_ctrl_set is difficult to understand because its argument may
not be explicit or complete about the SPEC_CTRL MSR bits the function
changes.

For example, the call x86_spec_ctrl_set(x86_spec_ctrl_base &
x86_spec_ctrl_mask) is made to enable the SSBD bit at boot, and
x86_spec_ctrl_set(SPEC_CTRL_FEATURE_DISABLE_IBRS) may also turn off
SSBD.

To make the function easier to understand, rework it to take the context
it's called in instead of a subset of the MSR bits to be changed.
Explain the bits modified for each context.

No functional change.  In particular, x86_spec_ctrl_set continues to
clear the SSBD MSR bit in the ssbd_userspace_selected() case when the
kernel becomes idle, in accordance with this section from
336996-Speculative-Execution-Side-Channel-Mitigations.pdf[1]:

"On Intel® Core™ and Intel® Xeon® processors that enable Intel®
Hyper-Threading Technology and do not support enhanced IBRS, setting
SSBD on a logical processor may impact the performance of a sibling
logical processor on the same core. Intel recommends that the SSBD MSR
bit be cleared when in an idle state on such processors."

[1] https://bugzilla.kernel.org/show_bug.cgi?id=199511

Signed-off-by: Daniel Jordan <daniel.m.jordan@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
(cherry picked from commit 44651cc127944465e6595a9362248e3bdf9c6d1c)

Orabug: 28271063

Signed-off-by: Anjali Kulkarni <anjali.k.kulkarni@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@oracle.com>
Signed-off-by: Brian Maly <brian.maly@oracle.com>