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RISC-V: Add defines for the SBI nested acceleration extension
authorAnup Patel <apatel@ventanamicro.com>
Sun, 20 Oct 2024 19:47:28 +0000 (01:17 +0530)
committerAnup Patel <anup@brainfault.org>
Mon, 28 Oct 2024 11:13:55 +0000 (16:43 +0530)
commit5daf89e73d77a5edb21c9b2d67a1b5bf02e61e5a
tree3e95c881475fac015d5b9657216e72b01269a6d1tree
parent15ff2ff3c3b99f986fde919dffab27007bbe35edcommit | diff
RISC-V: Add defines for the SBI nested acceleration extension

Add defines for the new SBI nested acceleration extension which was
ratified as part of the SBI v2.0 specification.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-8-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/sbi.h diff | blob | history
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