]> www.infradead.org Git - users/jedix/linux-maple.git/commit
x86/bugs: Rename _RDS to _SSBD
authorKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Wed, 9 May 2018 19:41:38 +0000 (21:41 +0200)
committerBrian Maly <brian.maly@oracle.com>
Mon, 21 May 2018 22:06:06 +0000 (18:06 -0400)
commit5af41fa4dbc10470cfaa49fc4ca15aa38404c5b2
tree428480d1e66e7136aabb1cf3582cabedccb1d0e6
parentb2eaac4a86ea4a7a0b1d7edb656ed1418c83952e
x86/bugs: Rename _RDS to _SSBD

Intel collateral will reference the SSB mitigation bit in IA32_SPEC_CTL[2]
as SSBD (Speculative Store Bypass Disable).

Hence changing it.

It is unclear yet what the MSR_IA32_ARCH_CAPABILITIES (0x10a) Bit(4) name
is going to be. Following the rename it would be SSBD_NO but that rolls out
to Speculative Store Bypass Disable No.

Also fixed the missing space in X86_FEATURE_AMD_SSBD.

[ tglx: Fixup x86_amd_rds_enable() and rds_tif_to_amd_ls_cfg() as well ]

OraBug: 28041771
CVE: CVE-2018-3639

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 9f65fb29374ee37856dbad847b4e121aab72b510)
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Mihai Carabas <mihai.carabas@oracle.com>
 Conflicts:
arch/x86/include/asm/cpufeatures.h
arch/x86/include/asm/msr-index.h
arch/x86/include/asm/spec-ctrl.h
arch/x86/include/asm/thread_info.h
arch/x86/kernel/cpu/bugs.c
arch/x86/kernel/cpu/intel.c
arch/x86/kernel/process.c
arch/x86/kvm/cpuid.c
arch/x86/kvm/vmx.c

Signed-off-by: Brian Maly <brian.maly@oracle.com>
Documentation/kernel-parameters.txt
arch/x86/include/asm/cpufeature.h
arch/x86/include/asm/spec-ctrl.h
arch/x86/include/asm/thread_info.h
arch/x86/include/uapi/asm/msr-index.h
arch/x86/kernel/cpu/amd.c
arch/x86/kernel/cpu/bugs_64.c
arch/x86/kernel/cpu/common.c
arch/x86/kernel/cpu/scattered.c
arch/x86/kernel/process.c
arch/x86/kvm/cpuid.c