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target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
authorTANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Thu, 19 Sep 2024 05:50:45 +0000 (13:50 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Oct 2024 01:22:07 +0000 (11:22 +1000)
commit58597bfeab45be303a4e514ce375e56b1b0c627e
tree98fbabbe3990819b1ea5bb3344ba416c76ef9f69tree
parent870589dcddcc542d88c5f0cdd9b2b43becc8a070commit | diff
target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU

Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240919055048.562-6-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_helper.c diff | blob | history
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