]> www.infradead.org Git - users/jedix/linux-maple.git/commit
drm/i915/pps: Store the power cycle delay without the +1
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 6 Nov 2024 21:58:52 +0000 (23:58 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 28 Nov 2024 15:59:50 +0000 (17:59 +0200)
commit57ecdc5521831b179d34109a74f993371fb2730e
treed9a9926cb4ee82b28641a17eec2a6495e7debc4b
parentda5bb8974c8a729aed4ce1c04fb582f13ddcb954
drm/i915/pps: Store the power cycle delay without the +1

The code initializing the power sequencing delays is a bit
hard to follow. One confusing thing is that we keep doing the
+/-1 adjustment for the hardware register value in several places.
Simplify this a bit by doing the adjustment only when reading or
writing the actual register.

This also matches how the LVDS code does things.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241106215859.25446-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_pps.c