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amd64_edac: Add a fix for Erratum 505
authorBorislav Petkov <borislav.petkov@amd.com>
Mon, 19 Sep 2011 15:34:45 +0000 (17:34 +0200)
committerMaxim Uvarov <maxim.uvarov@oracle.com>
Fri, 15 Jun 2012 20:43:14 +0000 (00:43 +0400)
commit553b8b3dfd8f43827bebfa5b4539c3f3fc43e782
tree99b08cc9bea340d089befe246c5ba69c72f82efftree
parent0dfb8684a846a7f82d81c763fce848c240f346f9commit | diff
amd64_edac: Add a fix for Erratum 505

When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
drivers/edac/amd64_edac.c diff | blob | history
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