]> www.infradead.org Git - users/dwmw2/qemu.git/commit
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
authorNicholas Piggin <npiggin@gmail.com>
Fri, 23 Feb 2024 12:34:56 +0000 (22:34 +1000)
committerNicholas Piggin <npiggin@gmail.com>
Thu, 25 Jul 2024 23:21:06 +0000 (09:21 +1000)
commit53f18b3ef2c3e898e7dae21a1f33f9e2f3eed764
tree5e519b722e936456792af87720369cf907a3b7f6
parent24c3caff995584342101a181af2eacd67129e5ec
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10

This implements a framework for an ADU unit model.

The ADU unit actually implements XSCOM, which is the bridge between MMIO
and PIB. However it also includes control and status registers and other
functions that are exposed as PIB (xscom) registers.

To keep things simple, pnv_xscom.c remains the XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.

So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
hw/ppc/meson.build
hw/ppc/pnv.c
hw/ppc/pnv_adu.c [new file with mode: 0644]
hw/ppc/pnv_xscom.c
hw/ppc/trace-events
include/hw/ppc/pnv_adu.h [new file with mode: 0644]
include/hw/ppc/pnv_chip.h
include/hw/ppc/pnv_xscom.h