]> www.infradead.org Git - users/jedix/linux-maple.git/commit
arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM
authorLukasz Czechowski <lukasz.czechowski@thaumatec.com>
Tue, 21 Jan 2025 12:56:03 +0000 (13:56 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 3 Feb 2025 08:14:34 +0000 (09:14 +0100)
commit4eee627ea59304cdd66c5d4194ef13486a6c44fc
tree7e65cc8cfff72b830827223aea6838ff2396cebc
parenta6a7cba17c544fb95d5a29ab9d9ed4503029cb29
arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM

In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for
uart5 cannot be used for the UART CTS/RTS, because they are already
allocated for different purposes. CTS pin is routed to SUS_S3#
signal, while RTS pin is used internally and is not available on
Q7 connector. Move definition of the pinctrl-0 property from
px30-ringneck-haikou.dts to px30-ringneck.dtsi.

This commit is a dependency to next commit in the patch series,
that disables DMA for uart5.

Cc: stable@vger.kernel.org
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250121125604.3115235-2-lukasz.czechowski@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi