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target/riscv: Align the AIA model to v1.0 ratified spec
authorTommy Wu <tommy.wu@sifive.com>
Wed, 16 Aug 2023 06:16:43 +0000 (23:16 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 11 Sep 2023 01:45:55 +0000 (11:45 +1000)
commit4df282335b3b13db30123fbcca050e4bf690a9d9
tree0e38d7ca62ac3201bddafe55b953ae15b9f66204tree
parent4e3adce1244e1ca30ec05874c3eca14911dc0825commit | diff
target/riscv: Align the AIA model to v1.0 ratified spec

According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.

Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/csr.c diff | blob | history
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