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drm/tegra: dpaux: Fix transfers larger than 4 bytes
authorThierry Reding <treding@nvidia.com>
Thu, 11 Jun 2015 16:33:48 +0000 (18:33 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 3 Aug 2015 16:29:08 +0000 (09:29 -0700)
commit3950be0f2d0feef1a8e647af82af861cd020c81e
tree0c17af760f022b382eeb59b487d2822fee3d220ftree
parentc8f84f037a61845643f4f86bf9ba49494a65e2c0commit | diff
drm/tegra: dpaux: Fix transfers larger than 4 bytes

commit 3c1dae0a07c651526f8e878d223a88f82caa5a50 upstream.

The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/tegra/dpaux.c diff | blob | history
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