]> www.infradead.org Git - users/jedix/linux-maple.git/commit
drm/i915/vrr: Compute vrr.vsync_{start, end} during full modeset
authorMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Thu, 30 Jan 2025 05:16:05 +0000 (10:46 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Thu, 30 Jan 2025 14:14:37 +0000 (19:44 +0530)
commit387f269e56eafa461a314a30b4e7f85625b2cba6
tree084b18ace6cb382c57b82805d00f5464afe825c8
parent2dbbbc1740388a8bc4a8237de0b009eecec8f998
drm/i915/vrr: Compute vrr.vsync_{start, end} during full modeset

vrr.vsync_{start,end} computation should not depend on
crtc_state->vrr.enable.

--v1:
 - Explain commit message more clearly [Jani]
 - Instead of tweaking to fastset use vrr.flipline while computing AS_SDP.
--v2:
 - Correct computation of vrr.vsync_start/end should not depend on
   vrr.enable.[ville]
 - vrr enable disable requirement should not obstruct by SDP enable
   disable requirements. [Ville]
--v3:
 - Create separate patch for crtc_state_dump [Ankit].

--v4:
 - Update commit message and header [Ankit].

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250130051609.1796524-3-mitulkumar.ajitkumar.golani@intel.com
drivers/gpu/drm/i915/display/intel_vrr.c