]> www.infradead.org Git - users/jedix/linux-maple.git/commit
dt-bindings: gpu: v3d: Add per-compatible register restrictions
authorMaíra Canal <mcanal@igalia.com>
Tue, 18 Mar 2025 01:01:10 +0000 (22:01 -0300)
committerMaíra Canal <mcanal@igalia.com>
Sun, 23 Mar 2025 14:06:01 +0000 (11:06 -0300)
commit38712c5281ac5f6f27058b825ca62ae69f2e2451
treeb484654700018465cdc3d9803b4887713a10c7ea
parent76dbd0973c555037931d2ed055a4a69e592caad4
dt-bindings: gpu: v3d: Add per-compatible register restrictions

In order to enforce per-SoC register rules, add per-compatible
restrictions. For example, V3D 3.3 (used in brcm,7268-v3d) has a cache
controller (GCA), which is not present in other V3D generations. Declaring
these differences helps ensure the DTB accurately reflect the hardware
design.

The example was using an incorrect order for the register names. This
commit corrects that by enforcing the order established in the register
items description.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250317-v3d-gpu-reset-fixes-v6-2-f3ee7717ed17@igalia.com
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml