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clk: renesas: r9a07g044: Add TSU clock and reset entry
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 20 Nov 2021 18:04:38 +0000 (18:04 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 26 Nov 2021 13:06:16 +0000 (14:06 +0100)
commit33b22d9c3272003a525ba2d6b7b851f3d4f30574
tree21229b27c57bbdd2e2cb7e1c39cd9c4dd4a331fctree
parent45177fc641f9de58180af158d1fac8defa99afcacommit | diff
clk: renesas: r9a07g044: Add TSU clock and reset entry

Add TSU clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211120180438.8351-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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