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drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport
authorJouni Högander <jouni.hogander@intel.com>
Mon, 18 Dec 2023 17:50:02 +0000 (19:50 +0200)
committerJouni Högander <jouni.hogander@intel.com>
Tue, 9 Jan 2024 13:39:59 +0000 (15:39 +0200)
commit3291bbb93e160e8b9b74ed0116738570f8744fe5
tree6c6e107e702cd38b7bc7d55e3a7ad903680ae7f2tree
parent7f85883e4a7b95559fb61cd202196ac8c8f857d7commit | diff
drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport

There is a new register used to configure selective update area size
for early transport.

Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area
carried in crtc_state->su_area.

Bspec: 68927

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-6-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_display.c diff | blob | history
drivers/gpu/drm/i915/display/intel_psr_regs.h diff | blob | history
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