x86/bugs: Rework spec_ctrl base and mask logic

x86/bugs: Rework spec_ctrl base and mask logic

x86_spec_ctrL_mask is intended to mask out bits from a MSR_SPEC_CTRL value
which are not to be modified. However the implementation is not really used
and the bitmask was inverted to make a check easier, which was removed in
"x86/bugs: Remove x86_spec_ctrl_set()"

Aside of that it is missing the STIBP bit if it is supported by the
platform, so if the mask would be used in x86_virt_spec_ctrl() then it
would prevent a guest from setting STIBP.

Add the STIBP bit if supported and use the mask in x86_virt_spec_ctrl() to
sanitize the value which is supplied by the guest.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Orabug: 28063992
CVE: CVE-2018-3639

(cherry picked from commit be6fcb54)
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Signed-off-by: Brian Maly <brian.maly@oracle.com>
Conflicts:
	arch/x86/kernel/cpu/bugs.c

[Konrad:
 As we have the IBRS support and boy that makes it double hard.
 The first part of this patch is to invert the mask, no biggie.

 But the mask for the IBRS mode (that is - we want to set SPEC_CTRL
 MSR to 1<<0 in kernel space, but in user-space we want it to be
 1<<1) didn't set the SSBD bit as we should not set the SSBD
 in kernel mode. But with the inversion that is OK.

 Next part is the two values - x86_spec_ctrl_base and x86_spec_ctrl_priv.

 The x86_spec_ctrl_base is what userspace is going to have (so
 tack on SSBD), and x86_spec_ctrl_priv what runs in kernel (so
 tack on IBRS, but _NOT_ SSBD).

 That means the whole logic of filtering the supported SPEC_CTRL
 value depending on what the host supports should be seeded
 with x86_spec_ctrl_priv.

 With all that the logic works - we end up ANDing our mask
 and what we can support (and the initial boot-time value of the
 MSR), and then ORing what the guest wants with our mask.

 All the while supporting any other bits in the SPEC_CTRL that
 may come in the future.

 And this logic is fine on AMD too - where the SSBD bit does not
 show up in the SPEC_CTRL mask

P.S.
To make it more fun the x86_spec_ctrl_priv |= IBRS is set in a
header (see set_ibrs_inuse).]

Signed-off-by: Brian Maly <brian.maly@oracle.com>