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drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide
authorJouni Högander <jouni.hogander@intel.com>
Fri, 17 May 2024 07:30:04 +0000 (10:30 +0300)
committerJouni Högander <jouni.hogander@intel.com>
Mon, 20 May 2024 04:34:45 +0000 (07:34 +0300)
commit30dee753ca0a1b565da5eec8d0686315f595d171
treef0c42b4e0c208288da4d08453ee79a8848c58488tree
parent45430e7b7c8de9ed910d99cc8906db3db5a1334dcommit | diff
drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide

On LunarLake  PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this
into account when enabling PSR2_CTL.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_psr.c diff | blob | history
drivers/gpu/drm/i915/display/intel_psr_regs.h diff | blob | history
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