]> www.infradead.org Git - users/jedix/linux-maple.git/commit
cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()
authorAlejandro Lucero <alucerop@amd.com>
Tue, 3 Dec 2024 16:21:12 +0000 (16:21 +0000)
committerDave Jiang <dave.jiang@intel.com>
Thu, 2 Jan 2025 20:09:13 +0000 (13:09 -0700)
commit2f84d072bdcb7d6ec66cc4d0de9f37a3dc394cd2
tree4c10abc8ef2935830132db5b21bbbdf7b7ac8398
parentc8e88de1b44e58cacdef41ea9aaa78fca35f1357
cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()

In cxl_dvsec_rr_decode() the pci driver expects to retrieve a cxlds,
struct cxl_dev_state, from the driver_data field of struct device.
While that works for Type 3, drivers for Type 1/2 devices may not
put a cxlds in the driver_data field.

In preparation for supporting Type 1/2 devices, replace parameter
'struct device' with 'struct cxl_dev_state' in cxl_dvsec_rr_decode().

Remove the unused parameter 'cxl_port' in cxl_dvsec_rr_decode().

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20241203162112.5088-1-alucerop@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/pci.c
drivers/cxl/cxl.h
drivers/cxl/port.c
tools/testing/cxl/test/mock.c