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target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
authorLeon Alrae <leon.alrae@imgtec.com>
Mon, 14 Sep 2015 12:51:31 +0000 (13:51 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Thu, 29 Oct 2015 16:16:44 +0000 (16:16 +0000)
commit2dcf7908d9e0274c08911400beb7ed14276bb170
tree31852b7fb89257870cb1ce5a96e9f703183efb72tree
parent7540a43a1d9de71fa7a53ccd2bb24a04e2aace41commit | diff
target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6

Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips/cpu.h diff | blob | history
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