]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: Add Smdbltrp ISA extension enable switch
authorClément Léger <cleger@rivosinc.com>
Thu, 16 Jan 2025 13:15:36 +0000 (14:15 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:35 +0000 (09:44 +1000)
commit2d8e8259287ced7c689a7c7fad67ad2a417e477c
treed415d0bdef0bd4899ed8b6dce6ddd637a7f63b47
parent00af7d53601b70f1353dabd1c87ffa260aafd27e
target/riscv: Add Smdbltrp ISA extension enable switch

Add the switch to enable the Smdbltrp ISA extension and disable it for
the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double
trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid
taking a double trap. OpenSBI does not currently support it so disable
it for the max cpu to avoid breaking regression tests.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250116131539.2475785-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/tcg/tcg-cpu.c