Add surprise removal block test

Add surprise removal block test

This test is for PCI devices in a surprise remove capable slot and tests
how well the drivers and kernel handle losing the link to that device.

The test finds the PCI Express Capability register of the pci slot a block
device is in, then at offset 0x10 (the Link Control Register) writes a 1
to bit 4 (Link Disable). This occurs unbeknownst to any of the drivers,
just like a surprise removal. Drivers will find out about this through
the pcie hotplug handler, at which point it's too late to communicate
with the device, therfore testing how well we cope with the condition.

The link is reenabled at the end of the test.

Note, this is currently incompatible with NVMe Subsystems when
CONFIG_NVME_MULTIPATH since the /dev/nvme*n* names don't have a pci
parent in sysfs.

Signed-off-by: Keith Busch <keith.busch@intel.com>