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spi: cadence: Add clock configuration for Marvell xSPI overlay
authorWitold Sadowski <wsadowski@marvell.com>
Wed, 24 Jul 2024 15:47:33 +0000 (08:47 -0700)
committerMark Brown <broonie@kernel.org>
Mon, 29 Jul 2024 00:19:26 +0000 (01:19 +0100)
commit26d34fdc49712ddbd42b11102f5d9d78a0f42097
tree4c167caa94ea72935fdbfc8de688b568ecabf409tree
parentb0d06169a7153f78b5356ca9e15cd836e43408ddcommit | diff
spi: cadence: Add clock configuration for Marvell xSPI overlay

Add support for clock divider. Divider block can disable, enable and
divide clock signal. Only 14 different divide ratios are avalible, from
6.25 up to 200MHz. For calculations use default Marvell system clock
value(800MHz).

Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
Link: https://patch.msgid.link/20240724154739.582367-4-wsadowski@marvell.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-cadence-xspi.c diff | blob | history
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