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spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.
authorNiravkumar L Rabara <niravkumar.l.rabara@intel.com>
Wed, 4 Dec 2024 06:33:38 +0000 (14:33 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 9 Dec 2024 13:06:24 +0000 (13:06 +0000)
commit25fb0e77b90e290a1ca30900d54c6a495eea65e2
tree1fe74179c9ecea3705c56caf2ead30565c996b3etree
parent0bb394067a792e7119abc9e0b7158ef19381f456commit | diff
spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.

STIG mode is enabled by default for less than 8 bytes data read/write.
STIG mode doesn't work with Altera SocFPGA platform due hardware
limitation.
Add a quirks to disable STIG mode for Altera SoCFPGA platform.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Link: https://patch.msgid.link/20241204063338.296959-1-niravkumar.l.rabara@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-cadence-quadspi.c diff | blob | history
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