sparc64: Add M7 hardware cache events into perf

sparc64: Add M7 hardware cache events into perf

Use the enhanced performance instrumentation provided
in the M7 to enable the following hardware cache
events in perf.

L1-dcache-load-misses
L1-dcache-loads
L1-dcache-prefetches
L1-dcache-store-misses
L1-dcache-stores
L1-icache-load-misses
L1-icache-loads
L1-icache-prefetches
LLC-load-misses
LLC-loads
LLC-prefetches
LLC-store-misses
LLC-stores
branch-load-misses
dTLB-load-misses
dTLB-store-misses
iTLB-load-misses

Orabug: 24621144

Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
(cherry picked from commit b1d3b6ce6d4a3e5cf88a16c1a99bf37e0b805131)
(cherry picked from commit 16f97e434978b46f8b92d911b907478a4fb3d00a)
Signed-off-by: Allen Pais <allen.pais@oracle.com>