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phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe
authorKrishna chaitanya chundru <quic_krichai@quicinc.com>
Fri, 22 Nov 2024 02:33:10 +0000 (10:33 +0800)
committerVinod Koul <vkoul@kernel.org>
Wed, 4 Dec 2024 13:41:17 +0000 (19:11 +0530)
commit21364b0fe378646fa301f29f714140a1f465561b
tree96f28a7dd82ffc3ce672184ab6c41c7e677dde9dtree
parent1e889f2bd8373229ce48be5860b8383e75393e13commit | diff
phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe

Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241122023314.1616353-3-quic_ziyuzhan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c diff | blob | history
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h diff | blob | history
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