]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: Add zcmop extension
authorLIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Tue, 9 Jul 2024 11:36:44 +0000 (19:36 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 18 Jul 2024 02:00:42 +0000 (12:00 +1000)
commit197e4d29889453760c74763662e3812d0ec7a645
treeba5e11138a311c69263aa8707da8845fdb2f4513
parentd98883d127d0029532601e9ca6832dfcb3ee2ca0
target/riscv: Add zcmop extension

Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
the reserved encoding space corresponding to C.LUI xn, 0.

Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions
are defined to not write any register.

In current implementation, C.MOP.n only has an check function, without any
other more behavior.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Message-ID: <20240709113652.1239-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h
target/riscv/insn16.decode
target/riscv/insn_trans/trans_rvzcmop.c.inc [new file with mode: 0644]
target/riscv/tcg/tcg-cpu.c
target/riscv/translate.c