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RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
authorPalmer Dabbelt <palmer@sifive.com>
Wed, 25 Jul 2018 00:17:14 +0000 (17:17 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 23 Oct 2018 00:37:41 +0000 (17:37 -0700)
commit1760debb51f73ed3e089c8d4e847554901dee4bb
tree9513702413d63d775e848257dfe76d3a84b6a7b9tree
parent84df9525b0c27f3ebc2ebb1864fa62a97fdedb7dcommit | diff
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/cacheinfo.c diff | blob | history
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