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target/riscv: Add CSR defines for RISC-V PM extension
authorAlexey Baturo <baturo.alexey@gmail.com>
Mon, 25 Oct 2021 17:36:03 +0000 (20:36 +0300)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 28 Oct 2021 04:39:23 +0000 (14:39 +1000)
commit138b5c5f8f5abec5acc18d2a256f0a082dc51ef5
treece971cf84a4a2f181ef4f0b42c94ff28587a7fa7tree
parent53dcea58b8ab150ab034f9c19074c5f74d6ca41ecommit | diff
target/riscv: Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h diff | blob | history
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