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clk: renesas: r9a07g043: Add LCDC clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Tue, 9 Jul 2024 13:51:42 +0000 (14:51 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 30 Jul 2024 08:28:39 +0000 (10:28 +0200)
commit10dfa837da4f5319ef6871c7cc7357da190c482f
tree059c23f5f74e72a6566f7ba6058e017aede7fe69tree
parent23319333146fb856f6e767f419830f6d7114eefccommit | diff
clk: renesas: r9a07g043: Add LCDC clock and reset entries

Add LCDC clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240709135152.185042-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | history
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