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perf/x86: Hybrid PMU support for hardware cache event
authorKan Liang <kan.liang@linux.intel.com>
Mon, 12 Apr 2021 14:30:48 +0000 (07:30 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Mon, 19 Apr 2021 18:03:25 +0000 (20:03 +0200)
commit0d18f2dfead8dd63bf1186c9ef38528d6a615a55
tree5dba9ccd7d54ca4a549bc2cb0180dec52e5c0fa9tree
parenteaacf07d1116f6bf3b93b265515fccf2301097f2commit | diff
perf/x86: Hybrid PMU support for hardware cache event

The hardware cache events are different among hybrid PMUs. Each hybrid
PMU should have its own hw cache event table.

Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1618237865-33448-9-git-send-email-kan.liang@linux.intel.com
arch/x86/events/core.c diff | blob | history
arch/x86/events/perf_event.h diff | blob | history
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