]> www.infradead.org Git - users/dwmw2/linux.git/commit
drm/i915: Bump GLK CDCLK frequency when driving multiple pipes
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 31 Oct 2023 16:08:00 +0000 (18:08 +0200)
committerJani Nikula <jani.nikula@intel.com>
Mon, 6 Nov 2023 12:42:49 +0000 (14:42 +0200)
commit0cb89cd42fd22bbdec0b046c48f35775f5b88bdb
treea4f3c4b149c45eef62dafc6578ba355602ea5033
parent0ad755fb88bdb7452f976d97847a47dbf7496763
drm/i915: Bump GLK CDCLK frequency when driving multiple pipes

On GLK CDCLK frequency needs to be at least 2*96 MHz when accessing
the audio hardware. Currently we bump the CDCLK frequency up
temporarily (if not high enough already) whenever audio hardware
is being accessed, and drop it back down afterwards.

With a single active pipe this works just fine as we can switch
between all the valid CDCLK frequencies by changing the cd2x
divider, which doesn't require a full modeset. However with
multiple active pipes the cd2x divider trick no longer works,
and thus we end up blinking all displays off and back on.

To avoid this let's just bump the CDCLK frequency to >=2*96MHz
whenever multiple pipes are active. The downside is slightly
higher power consumption, but that seems like an acceptable
tradeoff. With a single active pipe we can stick to the current
more optiomal (from power comsumption POV) behaviour.

Cc: stable@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9599
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231031160800.18371-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit 451eaa1a614c911f5a51078dcb68022874e4cb12)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_cdclk.c