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clk: tegra: Don't enable PLLE HW sequencer at init
authorJC Kuo <jckuo@nvidia.com>
Wed, 20 Jan 2021 07:34:02 +0000 (15:34 +0800)
committerThierry Reding <treding@nvidia.com>
Wed, 24 Mar 2021 13:02:14 +0000 (14:02 +0100)
commit0c7ea2b1c850756140fef03bed0fbaf0957f120a
treea32863a42509224fa63a063185144946f80bb4b9tree
parent54443ef6f5d10d9c6bb17f1dbeea7eb8d5c9a839commit | diff
clk: tegra: Don't enable PLLE HW sequencer at init

PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
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