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clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tue, 12 Aug 2025 17:17:20 +0000 (18:17 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 20 Aug 2025 07:16:32 +0000 (09:16 +0200)
commit07e7ccd804dc2aac6f3f96129a86b02391b5002d
treedcdd803c5e59d6d5bd29f585459499387cbd6709tree
parent54653bb3ec83d1f717adab6108db82a3966d19eecommit | diff
clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5

Add asynchronous core clocks and module clocks for SCI channels 1
through 5 on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812171720.3245851-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g077-cpg.c diff | blob | history
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