]> www.infradead.org Git - users/jedix/linux-maple.git/commit
riscv: Add xtheadvector instruction definitions
authorCharlie Jenkins <charlie@rivosinc.com>
Thu, 14 Nov 2024 02:21:14 +0000 (18:21 -0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Sat, 18 Jan 2025 20:33:32 +0000 (12:33 -0800)
commit01e3313e34d0e3912a7031c217367df051603149
tree887cd11d053e3459e656acddd4e6f439fe1d58bb
parentb9a9314424512e536db5e54ff554c2f10759c657
riscv: Add xtheadvector instruction definitions

xtheadvector uses different encodings than standard vector for
vsetvli and vector loads/stores. Write the instruction formats to be
used in assembly code.

Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-8-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/vendor_extensions/thead.h