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   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _input_system_ctrl_defs_h
  16 #define _input_system_ctrl_defs_h
  17
  18 #define _INPUT_SYSTEM_CTRL_REG_ALIGN                    4  /* assuming 32 bit control bus width */
  19
  20 /* --------------------------------------------------*/
  21
  22 /* --------------------------------------------------*/
  23 /* REGISTER INFO */
  24 /* --------------------------------------------------*/
  25
  26 // Number of registers
  27 #define ISYS_CTRL_NOF_REGS                              23
  28
  29 // Register id's of MMIO slave accesible registers
  30 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID              0
  31 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID              1
  32 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID              2
  33 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID         3
  34 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID         4
  35 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID         5
  36 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID         6
  37 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID         7
  38 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID         8
  39 #define ISYS_CTRL_ACQ_START_ADDR_REG_ID                 9
  40 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID            10
  41 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID            11
  42 #define ISYS_CTRL_INIT_REG_ID                           12
  43 #define ISYS_CTRL_LAST_COMMAND_REG_ID                   13
  44 #define ISYS_CTRL_NEXT_COMMAND_REG_ID                   14
  45 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID               15
  46 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID               16
  47 #define ISYS_CTRL_FSM_STATE_INFO_REG_ID                 17
  48 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID          18
  49 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID          19
  50 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID          20
  51 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID             21
  52 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID    22
  53
  54 /* register reset value */
  55 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL           0
  56 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL           0
  57 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL           0
  58 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL      128
  59 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL      128
  60 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL      128
  61 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL      3
  62 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL      3
  63 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL      3
  64 #define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL              0
  65 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL         128
  66 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL         3
  67 #define ISYS_CTRL_INIT_REG_RSTVAL                        0
  68 #define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  69 #define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  70 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  71 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  72 #define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL              0
  73 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL       0
  74 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL       0
  75 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL       0
  76 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL          0
  77 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
  78
  79 /* register width value */
  80 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH            9
  81 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH            9
  82 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH            9
  83 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH       9
  84 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH       9
  85 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH       9
  86 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH       9
  87 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH       9
  88 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH       9
  89 #define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH               9
  90 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH          9
  91 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH          9
  92 #define ISYS_CTRL_INIT_REG_WIDTH                         3
  93 #define ISYS_CTRL_LAST_COMMAND_REG_WIDTH                 32    /* slave data width */
  94 #define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH                 32
  95 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH             32
  96 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH             32
  97 #define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH               32
  98 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH        32
  99 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH        32
 100 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH        32
 101 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH           32
 102 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH  1
 103
 104 /* bit definitions */
 105
 106 /* --------------------------------------------------*/
 107 /* TOKEN INFO */
 108 /* --------------------------------------------------*/
 109
 110 /*
 111 InpSysCaptFramesAcq  1/0  [3:0] - 'b0000
 112 [7:4] - CaptPortId,
 113            CaptA-'b0000
 114            CaptB-'b0001
 115            CaptC-'b0010
 116 [31:16] - NOF_frames
 117 InpSysCaptFrameExt  2/0  [3:0] - 'b0001'
 118 [7:4] - CaptPortId,
 119            'b0000 - CaptA
 120            'b0001 - CaptB
 121            'b0010 - CaptC
 122
 123   2/1  [31:0] - external capture address
 124 InpSysAcqFrame  2/0  [3:0] - 'b0010,
 125 [31:4] - NOF_ext_mem_words
 126   2/1  [31:0] - external memory read start address
 127 InpSysOverruleON  1/0  [3:0] - 'b0011,
 128 [7:4] - overrule port id (opid)
 129            'b0000 - CaptA
 130            'b0001 - CaptB
 131            'b0010 - CaptC
 132            'b0011 - Acq
 133            'b0100 - DMA
 134
 135 InpSysOverruleOFF  1/0  [3:0] - 'b0100,
 136 [7:4] - overrule port id (opid)
 137            'b0000 - CaptA
 138            'b0001 - CaptB
 139            'b0010 - CaptC
 140            'b0011 - Acq
 141            'b0100 - DMA
 142
 143 InpSysOverruleCmd  2/0  [3:0] - 'b0101,
 144 [7:4] - overrule port id (opid)
 145            'b0000 - CaptA
 146            'b0001 - CaptB
 147            'b0010 - CaptC
 148            'b0011 - Acq
 149            'b0100 - DMA
 150
 151   2/1  [31:0] - command token value for port opid
 152
 153 acknowledge tokens:
 154
 155 InpSysAckCFA  1/0   [3:0] - 'b0000
 156  [7:4] - CaptPortId,
 157            CaptA-'b0000
 158            CaptB- 'b0001
 159            CaptC-'b0010
 160  [31:16] - NOF_frames
 161 InpSysAckCFE  1/0  [3:0] - 'b0001'
 162 [7:4] - CaptPortId,
 163            'b0000 - CaptA
 164            'b0001 - CaptB
 165            'b0010 - CaptC
 166
 167 InpSysAckAF  1/0  [3:0] - 'b0010
 168 InpSysAckOverruleON  1/0  [3:0] - 'b0011,
 169 [7:4] - overrule port id (opid)
 170            'b0000 - CaptA
 171            'b0001 - CaptB
 172            'b0010 - CaptC
 173            'b0011 - Acq
 174            'b0100 - DMA
 175
 176 InpSysAckOverruleOFF  1/0  [3:0] - 'b0100,
 177 [7:4] - overrule port id (opid)
 178            'b0000 - CaptA
 179            'b0001 - CaptB
 180            'b0010 - CaptC
 181            'b0011 - Acq
 182            'b0100 - DMA
 183
 184 InpSysAckOverrule  2/0  [3:0] - 'b0101,
 185 [7:4] - overrule port id (opid)
 186            'b0000 - CaptA
 187            'b0001 - CaptB
 188            'b0010 - CaptC
 189            'b0011 - Acq
 190            'b0100 - DMA
 191
 192   2/1  [31:0] - acknowledge token value from port opid
 193
 194 */
 195
 196 /* Command and acknowledge tokens IDs */
 197 #define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID        0 /* 0000b */
 198 #define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID         1 /* 0001b */
 199 #define ISYS_CTRL_ACQ_FRAME_TOKEN_ID              2 /* 0010b */
 200 #define ISYS_CTRL_OVERRULE_ON_TOKEN_ID            3 /* 0011b */
 201 #define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID           4 /* 0100b */
 202 #define ISYS_CTRL_OVERRULE_TOKEN_ID               5 /* 0101b */
 203
 204 #define ISYS_CTRL_ACK_CFA_TOKEN_ID                0
 205 #define ISYS_CTRL_ACK_CFE_TOKEN_ID                1
 206 #define ISYS_CTRL_ACK_AF_TOKEN_ID                 2
 207 #define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID        3
 208 #define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID       4
 209 #define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID           5
 210 #define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID       6
 211
 212 #define ISYS_CTRL_TOKEN_ID_MSB                    3
 213 #define ISYS_CTRL_TOKEN_ID_LSB                    0
 214 #define ISYS_CTRL_PORT_ID_TOKEN_MSB               7
 215 #define ISYS_CTRL_PORT_ID_TOKEN_LSB               4
 216 #define ISYS_CTRL_NOF_CAPT_TOKEN_MSB              31
 217 #define ISYS_CTRL_NOF_CAPT_TOKEN_LSB              16
 218 #define ISYS_CTRL_NOF_EXT_TOKEN_MSB               31
 219 #define ISYS_CTRL_NOF_EXT_TOKEN_LSB               8
 220
 221 #define ISYS_CTRL_TOKEN_ID_IDX                    0
 222 #define ISYS_CTRL_TOKEN_ID_BITS                   (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
 223 #define ISYS_CTRL_PORT_ID_IDX                     (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
 224 #define ISYS_CTRL_PORT_ID_BITS                    (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
 225 #define ISYS_CTRL_NOF_CAPT_IDX                    ISYS_CTRL_NOF_CAPT_TOKEN_LSB
 226 #define ISYS_CTRL_NOF_CAPT_BITS                   (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
 227 #define ISYS_CTRL_NOF_EXT_IDX                     ISYS_CTRL_NOF_EXT_TOKEN_LSB
 228 #define ISYS_CTRL_NOF_EXT_BITS                    (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
 229
 230 #define ISYS_CTRL_PORT_ID_CAPT_A                  0 /* device ID for capture unit A      */
 231 #define ISYS_CTRL_PORT_ID_CAPT_B                  1 /* device ID for capture unit B      */
 232 #define ISYS_CTRL_PORT_ID_CAPT_C                  2 /* device ID for capture unit C      */
 233 #define ISYS_CTRL_PORT_ID_ACQUISITION             3 /* device ID for acquistion unit     */
 234 #define ISYS_CTRL_PORT_ID_DMA_CAPT_A              4 /* device ID for dma unit            */
 235 #define ISYS_CTRL_PORT_ID_DMA_CAPT_B              5 /* device ID for dma unit            */
 236 #define ISYS_CTRL_PORT_ID_DMA_CAPT_C              6 /* device ID for dma unit            */
 237 #define ISYS_CTRL_PORT_ID_DMA_ACQ                 7 /* device ID for dma unit            */
 238
 239 #define ISYS_CTRL_NO_ACQ_ACK                      16 /* no ack from acquisition unit */
 240 #define ISYS_CTRL_NO_DMA_ACK                      0
 241 #define ISYS_CTRL_NO_CAPT_ACK                     16
 242
 243 #endif /* _input_system_ctrl_defs_h */